A typical prior art liquid crystal display (LCD) panel is shown in FIG. 1. As shown, the LCD panel 10 comprises a display module 20 having a plurality of pixels 22 arranged in a two-dimensional array. These pixels are controlled and activated by a plurality of data lines D1, D2, . . . , Dn and a plurality of gate lines G1, G2, . . . , Gm. The data signal in each of the data lines is provided by a data driver integrated circuit (IC) 30 and the gate signal in each of the gate lines is provided by a gate driver IC 40. The construction and operation of the prior art display panel is well understood in the art.
Typically in the prior art as illustrated in FIGS. 2 and 3, each of the pixels 22 is associated with a number of capacitors including, for example, the capacitor Clc associated with and formed by the capacitance of the liquid crystal layer located between the upper and lower electrodes, an additional charge storage capacitor Cst which maintains the voltage Vpixel after the gate line signal Gate m has passed, and the capacitance Cgs associated with the gate terminal and the source terminal of the switching element (TFT). The total capacitance associated with a pixel in an LCD may vary due to the pixel size, the thickness of the liquid crystal layer, the size of the storage capacitor, and other variables known to those skilled in the art. In FIG. 2, both Clc and Cst are connected to a common voltage Vcom. In FIG. 3, Cst is connected to a gate line.
A prior art gate driver circuit in a gate driver IC generally designated 50 and as illustrated in FIG. 4, is commonly used to provide gate line signals for driving a row of the LCD pixels. The gate driver circuit 50 typically operates rail-to-rail between Vgh and Vgl voltage potentials and has a gate input 52 and an output 54 to drive the gate of the LCD pixel switching element (TFT). The gate driver circuit 50 is made up of a PMOS switching element 56 and an NMOS switching element 58 constructed in complementary form on a silicon wafer in a well known configuration. The gate driver circuit 50 operates in a well known manner. When the signal at the input 52 is high, it causes the PMOS switching element 56 to conduct due to the formation of a P-channel while the NMOS switching element 58 remains “OFF” or non-conducting. In this state, the voltage level at the output 54 is high and the equivalent circuit of the gate driver circuit 50 is as shown in FIG. 5A. When the signal at the input 52 is low, it causes the NMOS switching element 58 to conduct due to the formation of a N-channel while the PMOS switching element 56 is “OFF” or non-conducting. In this state, the voltage level at the output 54 is low and equivalent circuit is as shown in FIG. 5B. Rm1 and Rm2 are the internal impedance of M1 and the internal impedance of M2, respectively.
Now as the load presented to the gate driver output varies with the number of pixels along the same gate line and the impedance of the individual pixels, it can be seen that there will be longer charge time required for the capacitors because there is less current available to charge the capacitors in a given time interval.
Ideally, it would be desirable to increase the driving capacity of the gate driver in order to reduce the gate delay time when the load increases. Furthermore, it would be desirable not to have a gate driver with excessive driving capacity when the load is not heavy such as when the gate driver is used to drive a small the LCD panel.
In a display panel with high resolution and a high frame rate, it is important to charge the pixel capacitance within a certain time. However, as seen from the prior art described above, the driving load capacity of a conventional prior art gate driver IC is fixed. When the conventional prior art gate driver IC is used in a different display panel for example as shown in FIG. 12A, the difference in the load on a gate line may affect the viewing quality of the display panel because the pixel capacitance takes longer to charge as shown by the charging waveform in FIG. 12B. In FIG. 12A, Y1-Y4 are separate gate driver ICs 40, each of which is used to drive a number of gate lines in a TFT-LCD panel 20, and the input control signal is provided to the gate driver ICs 40 so that the gate lines in the LCD panel are scanned in a sequential order, for example.
If we can widen the adjustment range of the driving capacity of a gate driver IC, the same IC can be used in display panels of different sizes or in the display panels of different designs. As such, it would not be necessary to produce different gate driver IC's in order to meet the driving need of different display panels.
Accordingly, it is an object of the present invention to provide an LCD gate driver circuitry having an adjustable current driving capacity for use with different display panels.